1. Field of the Invention
The present invention is related to a liquid crystal display device and method for driving the same, and more particularly, to a liquid crystal display device capable of reducing image flicker and method for driving the same.
2. Description of the Prior Art
Liquid crystals display (LCD) devices, characterized in low radiation, small size and low power consumption, have gradually replaced traditional cathode ray tube (CRT) devices and been widely used in electronic products, such as notebook computers, personal digital assistants (PDAs), flat panel TVs, or mobile phones. In traditional LCD devices, a source driver and a gate driver are used for driving the pixels of the panel in order to display images. Since the source driver is more expensive than the gate driver, LCD devices adopting half source driver (HSD) structure have been developed in order to reduce the number of source drivers. In other words, for the same amount of pixels, the manufacturing cost can be reduced by halving the number of data lines receiving signals from the source driver and doubling the number of gate lines receiving signals from the gate driver.
FIG. 1 is a prior art LCD device 100 which adopts HSD structure. The LCD device 100 includes a timing controller 130, a source driver 110, a gate driver 120, a plurality of data lines DL1-DLm, a plurality of gate lines GL1-GLn, and a pixel matrix. The pixel matrix includes a plurality of pixel units PXL and PXR each having a thin film transistor (TFT) switch, a liquid crystal capacitor CLC and a storage capacitor CST, and respectively coupled to a corresponding data line, a corresponding gate line and a common node. The timing controller 130 can generate control signals YOE and YV1C, input clock signals CK and CKB or an output enable signal OE for operating the source driver 110 and the gate driver 20. The source driver 110 can generate data driving signals SD1-SDm corresponding to display images. If the gate driver 120 is an external driving circuit, the gate driving signals SG1-SGn for turning on the TFT switches are generated according to the control signals YOE and YV1C; if the gate driver 120 is fabricated using gate on array (GOA) technique, the gate driving signals SG1-SGn are generated according to the input clock signals CK,CKB and the output enable signal OE.
When the TFT switch is turned off, the pixel electrode is not connected to any voltage source and thus has a floating level. Any voltage variation around the pixel electrode is coupled to the pixel electrode via its parasite capacitance, which in turn influences the voltages applied to the liquid crystal capacitor CLC and the storage capacitor CST. The feed-through voltage VFD due to voltage variations caused by parasite capacitance can be represented by the following equation:VFD=[CGD/(CLC+CST+CGD)]*ΔVG=K*ΔVG 
CGD represents the parasite capacitance between the gate and the drain of the TFT switch. K represents the percentage of CGD which contributes to the overall parasite capacitance. ΔVG represents the gate voltage difference caused by a gate driving signal when turning off a corresponding TFT switch. The parasite capacitance is an inherent characteristic of the TFT switch. In order to effectively reduce image flicker, the gate voltage difference ΔVG needs to be lowered first before adjusting the common voltage Vcom for compensating the feed-through voltage VFD.
FIGS. 2 and 3 are diagrams illustrating methods for driving the prior art LCD device 100. FIG. 2 shows the waveforms of the control signal YOE and the gate driving signals SG1-SG4 when the gate driver 120 is an external circuit. FIG. 3 shows the waveforms of the clock signals CK, CKB, O_CK, O_CKB, the output enable signal OE and the gate driving signals SG1-SG4 when the gate driver 120 is fabricated using GOA technique.
In the driving method depicted in FIG. 2, the length of the enable period in the gate driving signals SG1-SG4 is determined by the pulse width of the control signal YOE, and the length of the signal falling time in the gate driving signals SG1-SG4 is determined by the signal falling start point of the control signals YOE and YV1C. In each period, the control signal YOE remains at high level for a constant length, and the waveform of the control signal YV1C starts to fall at the same point. Therefore, the gate driving signals SG1-SG4 result in an identical gate voltage difference ΔVG′ when turning off corresponding TFT switches. As previously stated, the feed-through voltage is proportional to the gate voltage difference. Since the gate voltage difference ΔVG′ after voltage trimming is smaller than the gate voltage difference ΔVG without voltage trimming, the effect of the feed-through voltage can be compensated.
In the driving method depicted in FIG. 3, the clock signals CK and CKB having opposite phases switch between high/low voltage levels based on a predetermined period which determines the length of the enable period in the gate driving signals SG1-SG4. When the output enable signal OE is at high level, the gate driver 120 outputs the clock signals CK and CKB for providing the corresponding clock signals O_CK and O_CKB. When the output enable signal OE is at low level, the gate driver 120 stops outputting the clock signals CK and CKB. Charge-sharing is then performed between the clock signals O_CK and O_CKB, thereby achieving voltage trimming at the signal falling edge. The gate driving signals SG1-SG4 can thus be provided according to the clock signals O_CK and O_CKB after charge-sharing. In each period, the output enable signal OE remains at low level for a constant length T, the degree of voltage trimming in the gate driving signals SG1-SG4 is identical. Therefore, the gate driving signals SG1-SG4 result in an identical gate voltage difference ΔVG′ when turning off corresponding TFT switches. As previously stated, the feed-through voltage is proportional to the gate voltage difference. Since the gate voltage difference ΔVG′ after voltage trimming is smaller than the gate voltage difference ΔVG without voltage trimming, the effect of the feed-through voltage can be compensated.
In the prior art LCD device 100, the pixel units are disposed on both sides of each data line, wherein the pixel units PXL disposed on the left side of the data lines are controlled by the gate driving signals SG1, SG3, . . . , SGn-1 transmitted from the odd-numbered gate lines, while the pixel units PXR disposed on the right side of the data lines are controlled by the gate driving signals SG2, SG4, . . . , SGn transmitted from the even-numbered gate lines. Normally adopting different designs, these two types of pixel units PXL and PXR have different CLC, CST, CGS or CGD, and the value of the feed-through voltage VFD also varies. Even if the two types of pixel units PXL and PXR adopt the same design, the value of the feed-through voltage VFD may also vary due to characteristic shift caused by manufacturing process deviations, For example, the process shift between the first metal layer M1 and the second metal layer M2 may result in different CGD values of the pixel units PXL and PXR.
In the driving methods depicted in FIGS. 2 and 3, the gate voltage difference of each pixel is lowered by the same degree. Since each pixel has different feed-through voltage, image flicker can not be effectively reduced by adjusting the common voltage Vcom.